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LTC4306 4-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering
FEATURES

DESCRIPTIO
1:4 2-Wire Multiplexer/Switch Connect SDA and SCL Lines with 2-Wire Bus Commands Supply Independent Bidirectional Buffer for SDA and SCL Lines Increases Fan-Out Programmable Disconnect from Stuck Bus Compatible with I2C and SMBus Standards Rise Time Accelerator Circuitry SMBus Compatible ALERT Response Protocol Two General Purpose Inputs-Outputs Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane 10kV Human Body Model ESD Ruggedness 24-Lead QFN (4mm x 5mm) and SSOP Packages
The LTC(R)4306 is a 4-channel, 2-wire bus multiplexer with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Through software control, the LTC4306 connects the upstream 2-wire bus to any desired combination of downstream buses. Each channel can be pulled up to a supply voltage ranging from 2.2V to 5.5V, independent of the LTC4306 supply voltage. The downstream channels are also provided with ALERT1-ALERT4 inputs for fault reporting. Programmable timeout circuitry disconnects the downstream buses if the bus is stuck low. When activated, rise time accelerators source currents into the 2-wire bus pins to reduce rise time. Driving the ENABLE pin low restores all features to their default states. Three address pins provide 27 distinct addresses. The LTC4306 is available in 24-lead QFN (4mm x 5mm) and SSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending.
APPLICATIO S

Nested Addressing 5V/3.3V Level Translator Capacitance Buffer/Bus Extender
TYPICAL APPLICATIO
2.5V 3.3V
A Level Shifting and Nested Addressing Application I2C Bus Waveforms
VCC = 3.3V
0.01F 10k 10k 10k VCC MICROCONTROLLER SCLIN SDAIN ALERT SCL1 SDA1 ALERT1 5V SFP MODULE 1 ADDRESS = 1111 000 LTC4306 10k 10k 10k
SCLIN 2V/DIV
SCL1 2V/DIV
* * *
10k
10k
10k SFP MODULE 4
SCL4 2V/DIV 500ns/DIV VCARD4 = 5V
ADR2 ADR1 ADR0 GND
SCL4 SDA4 ALERT4
4306 TA01a
ADDRESS = 1111 000
ADDRESS = 1000 100
U
VBACK = 2.5V VCARD1 = 3.3V
4306 TA01b
U
U
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1
LTC4306
ABSOLUTE AXI U RATI GS
Supply Voltage (VCC) ................................... -0.3V to 7V Input Voltages (ADR0, ADR1, ADR2, ENABLE, ALERT1, ALERT2, ALERT3, ALERT4) .................................................. -0.3V to 7V Output Voltages (ALERT, READY) ............... -0.3V to 7V Input/Output Voltages (SDAIN, SCLIN, SCL1, SDA1, SCL2, SDA2, SCL3, SDA3, SCL4, SDA4, GPIO1, GPIO2) ........ -0.3V to 7V Output Sink Currents (SDAIN, SCLIN, SCL1-4, SDA1-4, GPI01-2, ALERT, READY) ..................................... 10mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ALERT2
SDA3
SDA2
SCL3
SCL2
ORDER PART NUMBER
19 ALERT3 18 ALERT1 17 SDA1
24 23 22 21 20 ALERT 1 SDAIN 2 GND 3 SCLIN 4 ENABLE 5 VCC 6 ALERT4 7 8 9 10 11 12 25
LTC4306CUFD LTC4306IUFD
16 SCL1 15 SCL4 14 SDA4 13 READY
UF PART MARKING* 4306
ADR0
ADR1
GPIO1
GPI02
ADR2
UFD PACKAGE 24-LEAD (4mm x 5mm) PLASTIC QFN
EXPOSED PAD (PIN 25), PCB CONNECTION OPTIONAL MUST BE CONNECTED TO THE PCB TO OBTAIN JA = 43C/W OTHERWISE JA = 140C/W. TJMAX = 125C
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
SYMBOL VCC ICC ICC ENABLE = 0V VUVLOU PARAMETER Input Supply Range Input Supply Current Input Supply Current UVLO Upper Threshold Voltage Power Supply/Start-Up
The denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise noted.
CONDITIONS
Downstream Connected, SCL Bus Low, SDA Bus High, VCC = 5.5V VENABLE = 0V, VCC = 5.5V
2
U
U
W
WW U
W
(Note 1)
Operating Temperature Range LTC4306C ............................................... 0C to 70C LTC4306I ............................................. -40C to 85C Storage Temperature Range SSOP ................................................. -65C to 150C QFN ................................................... -65C to 125C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300C
TOP VIEW SCL3 SDA3 ALERT SDAIN GND SCLIN ENABLE VCC ALERT4 1 2 3 4 5 6 7 8 9 24 ALERT2 23 SCL2 22 SDA2 21 ALERT3 20 ALERT1 19 SDA1 18 SCL1 17 SCL4 16 SDA4 15 READY 14 ADR2 13 ADR1
ORDER PART NUMBER LTC4306CGN LTC4306IGN
GPI01 10 GPI02 11 ADR0 12
GN PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 125C, JA = 85C/W
MIN 2.7
TYP
MAX 5.5
UNITS V mA mA V
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5.2 1.25 2.3 2.5
8 2.5 2.7
LTC4306
The denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise noted.
SYMBOL VUVLOHYST VTH EN VENHYST tPHLEN tPLHEN IINEN VLOWREADY IOFFREADY VOS,BUF VOS,UP-BUF VOS,DOWN-BUF VOL PARAMETER UVLO Threshold Hysteresis Voltage ENABLE Falling Threshold Voltage ENABLE Threshold Hysteresis Voltage ENABLE Delay, On-Off ENABLE Delay, Off-On ENABLE Input Leakage Current READY Pin Logic Low Output Voltage READY Off State Input Leakage Current Buffer Offset Voltage Upstream Buffer Offset Voltage VIN, BUFFER = 0V Downstream Buffer Offset Voltage VIN, BUFFER = 0V Output Low Voltage, VIN,BUFFER = 0V Output Low Voltage, VIN,BUFFER = 0.2V VIL,MAX VTHSDA,SCL ILEAK Buffer Input Logic Low Voltage Downstream SDA, SCL Logic Threshold Voltage Input Leakage Current SDA, SCL Pins; VCC = 0V to 5.5V; Buffers Inactive SDAIN, SCLIN, SDA1-4, SCL1-4 Pins SDAIN, SCLIN, SDA1-4, SCL1-4 Pins SDAIN, SCLIN, SDA1-4, SCL1-4 Pins (Note 3)
ELECTRICAL CHARACTERISTICS
CONDITIONS

MIN 100 0.8
TYP 175 1.0 60 60 20
MAX 250 1.2
UNITS mV V mV ns ns
VENABLE = 0V, 5.5V, VCC = 5.5V IPULL-UP = 3mA, VCC = 2.7V VREADY = 0V, 5.5V, VCC = 5.5V RBUS = 10k, VCC = 2.7V, 5.5V (Note 4) VCC = 2.7V, RBUS = 2.7k (Note 4) VCC = 5.5V, RBUS = 2.7k (Note 4) VCC = 2.7V, RBUS = 2.7k (Note 4) VCC = 5.5V, RBUS = 2.7k (Note 4) SDA, SCL Pins; ISINK = 4mA, VCC = 3V, 5.5V SDA, SCL Pins; ISINK = 500A, VCC = 2.7V, 5.5V VCC = 2.7V, 5.5V

0 0.18 0 25 40 70 60 80 60 80 110 110 140
1 0.4 1 100 120 150 160 200 400 320
A V A mV mV mV mV mV mV mV V V A
Upstream-Downstream Buffers
0.4 0.8
0.52 1.0 0
0.64 1.2 5
Rise Time Accelerators VSDA,SCL slew VRISE,DC IBOOST GPIOs VGPIO(TH) VGPIO(OL) VGPIO(OH) IGPIO(IN) VTIMER(L) VTIMER(HYST) TTIMER1 TTIMER2 TTIMER3 ALERT VALERT(OL) IOFF,ALERT IIN,ALERT1-4 ALERT Output Low Voltage ALERT Off State Input Leakage Current ALERT1-ALERT4 Input Current IALERT = 3mA, VCC = 2.7V VALERT = 0V, 5.5V VALERT1-4 = 0V, 5.5V

Minimum Slew Requirement to Activate Rise Time Accelerator Currents Rise Time Accelerator DC Threshold Voltage Rise Time Accelerator Pull-Up Current

0.4 0.7 4 0.8 5.5
0.8 1
V/s V mA
GPIO Pin Input Threshold GPIO Pin Output Low Voltage GPIO Pin Output High Voltage GPIO Pin Input Leakage Current Stuck Low Falling Threshold Voltage Stuck Low Threshold Hysteresis Voltage Timeout Time #1 Timeout Time #2 Timeout Time #3 TIMSET1,0 = 01 TIMSET1,0 = 10 TIMSET1,0 = 11 IGPIO = 5mA, VCC = 2.7V IGPIO = -200A, VCC = 2.7V VGPIO = 0V, 5.5V, VCC = 5.5V VCC = 2.7V, 5.5V
0.8 VCC - 0.3
1 0.2 0
1.2 0.4 1 0.64 35 17.5 8.75 0.4 1 1
V V V A V mV ms ms ms V A A
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Stuck Low Timeout Circuitry 0.4 25 12.5 6.25 0.52 80 30 15 7.5 0.2 0 0
3
LTC4306
The denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise noted.
SYMBOL VALERT1-4(IN) VALERT1-4(HY) I2C Interface VADR(H) VADR(L) IADR(IN, L) IADR(FLOAT) IADR(IN, H) ADR0-2 Input High Voltage ADR0-2 Input Low Voltage ADR0-2 Logic Low Input Current ADRO-2 Allowed Input Current ADR0-2 Logic High Input Current ADR0-2 = 0V, VCC = 5.5V VCC = 2.7V, 5.5V (Note 5) ADR0-2 = VCC = 5.5V VCC = 5.5V

ELECTRICAL CHARACTERISTICS
PARAMETER ALERT1-ALERT4 Pin Input Falling Threshold Voltages ALERT1-ALERT4 Pin Input Threshold Hysteresis Voltages
CONDITIONS
MIN 0.8
TYP 1.0 80
MAX 1.2
UNITS V mV
0.75 * VCC 0.9 * VCC 0.1 * VCC 0.25 * VCC -30 5 30 1.4 -60 13 60 1.6 30 80 1.8 -80
V V A A A V mV
VSDAIN,SCLIN(TH) SDAIN, SCLIN Input Falling Threshold Voltages VSDAIN,SCLIN(HY) SDAIN, SCLIN Hysteresis ISDAIN,SCLIN(OH) SDAIN, SCLIN Input Current CIN VSDAIN(OL) fSCL tBUF tHD,STA tSU,STA tSU,STO tHD,DATI tHD,DATO tSU,DAT tf tSP SDA, SCL Input Capacitance SDAIN Output Low Voltage Maximum SCL Clock Frequency Hold Time After (Repeated) Start Condition Repeated Start Condition Set-up Time Stop Condition Set-up Time Data Hold Time Input Data Hold Time Output Data Set-up Time SCL, SDA Fall Times Pulse Width of Spikes Suppressed by the Input Filter
SCL, SDA = VCC (Note 2) ISDA = 4mA, VCC = 2.7V (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2)

0 6 0.2 400 0.75 45 -30 -30 -25 300 20 + 0.1 * CBUS 50 150 600 50
5 0.4
A pF V kHz
I2C Interface Timing Bus Free Time Between Stop/Start Condition (Note 2) 1.3 100 0 0 0 900 100 300 250 s ns ns ns ns ns ns ns ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design and not subject to test. Note 3: The boosted pull-up currents are regulated to prevent excessively fast edges for light loads. See the Typical Performance Characteristics for rise time as a function of VCC and parasitic bus capacitance CBUS and for IBOOST as a function of VCC and temperature. Note 4: When a logic low voltage, VLOW, is forced on one side of the Upstream-Downstream Buffers, the voltage on the other side is regulated
to a voltage VLOW2 = VLOW + VOS, where VOS is a positive offset voltage. VOS,UP-BUF is the offset voltage when the LTC4306 is driving the upstream pin (e.g., SDAIN) and VOS,DOWN-BUF is the offset voltage when the LTC4306 is driving the downstream pin (e.g., SDA1). See the Typical Performance Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a function of VCC and bus pull-up current. Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage currents up to IADR(FLOAT) and still convert the address correctly.
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LTC4306 TYPICAL PERFOR A CE CHARACTERISTICS
Buffer Circuitry tPHL vs Temperature
120 100 VCC = 3.3V
tPHL (ns)
VCC = 5V 60 40 20 0 -50 -25
RISE TIME (ns)
150
VCC = 5V
CURRENT (mA)
80
50 25 75 0 TEMPERATURE (C)
VOS,UP-BUF vs Bus Pull-Up Current
180 160 250 140 120
VOS (mV)
VOS (mV)
VCC = 3.3V VCC = 5V
100 80 60 40
20 0 0 3 1 2 BUS PULL-UP CURRENT (mA) 0 4
4306 G04
Downstream RFET On Resistance vs VCC and Temperature
45 40 35 30
IBOOST (mA)
RON ()
VCC = 3.3V 25 20 15 VCC = 5V
10 5 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
UW
100
4306 G01
(TA = 25C, unless otherwise indicated)
Rise Time vs CBUS vs VCC
250 dV = 0.3V * VCC TO 0.7V * VCC RBUS = 10k VCC = 3.3V
ICC vs Temperature
6 VCC = 5V 5 4 3 2 1 UPSTREAM CONNECTED TO CHANNEL 1, SCL BUS LOW, SDA BUS HIGH 0 50 100 125 -50 -25 25 75 0 TEMPERATURE (C)
4306 G03
200
VCC = 3.3V
100
50
125
0
0
200 600 800 400 CAPACITANCE, CBUS (pF)
1000
4306 G02
VOS,DOWN-BUF vs Bus Pull-Up Current
300
200 VCC = 3.3V 150 VCC = 5V 100 50
0
1 2 3 BUS PULL-UP CURRENT (mA)
4
4306 G05
IBOOST vs Temperature
14 12 10 VCC = 5V 8 6 VCC = 3.3V 4 2 0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
4306 G06
4306 G07
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LTC4306
PI FU CTIO S (GN24 Package/UFD24 Package)
ALERT (Pin 3/Pin 1): Fault Alert Output. An open-drain output that is pulled low when a fault occurs to alert the host controller. The LTC4306 pulls ALERT low when any of the ALERT1-ALERT4 pins is low, when the 2-wire bus is stuck low, or when the Connection Requirement bit of Register 2 is low and a master tries to connect to a downstream channel that is low. See Operation section for the details of how ALERT is set and cleared. The LTC4306 is compatible with the SMBus Alert Response Address protocol. Connect a 10k resistor to a power supply voltage to provide the pull-up. Tie to ground if unused. SDAIN (Pin 4/Pin 2): Serial Bus Data Input and Output. Connect this pin to the SDA line on the master side. An external pull-up resistor or current source is required. GND (Pin 5/Pin 3): Device Ground. SCLIN (Pin 6/Pin 4): Serial Bus Clock Input. Connect this pin to the SCL line on the master side. An external pull-up resistor or current source is required. ENABLE (Pin 7/Pin 5): Digital Interface Enable and Register Reset. Driving ENABLE high enables I2C communication to the LTC4306. Driving this pin low disables I2C communication to the LTC4306 and resets the registers to their default state as shown in the Operation section. When ENABLE returns high, masters can read and write the LTC4306 again. If unused, tie ENABLE to VCC. VCC (Pin 8/Pin 6): Power Supply Voltage. Connect a bypass capacitor of at least 0.01F directly between VCC and GND for best results. GPIO1-GPIO2 (Pins 10, 11/Pins 8, 9): General Purpose Input/Output. These two pins can be used as logic inputs, open-drain outputs or push-pull outputs. The N-channel MOSFET pull-down devices are capable of driving LEDs. When used in input or open-drain output mode, the GPIOs can be pulled up to a supply voltage ranging from 1.5V to 5.5V independent of the VCC voltage. GPIOs default to a high impedance open-drain output mode. There are GPIO configuration and status bits in Register 1 and Register 2. Float if unused. ADR0-ADR2 (Pins 12, 13, 14/Pins 10, 11, 12): ThreeState Serial Bus Address Inputs. Each pin may be floated, tied to ground or tied to VCC. There are therefore 27 possible addresses. See Table 1 in applications information. When the pins are floated, they can tolerate 5A of leakage current and still convert the address correctly. READY (Pin 15/Pin 13): Connection Ready Digital Output. An N-channel MOSFET open-drain output transistor that pulls down when none of the downstream channels is connected to the upstream bus and turns off when one or more downstream channels is connected to the upstream bus. Connect a 10k resistor to a power supply voltage to provide the pull-up. Tie to ground if unused. SCL1-SCL4 (Pins 18, 23, 1, 17/Pins 16, 21, 23, 15): Serial Bus Clock Outputs Channels 1-4. Connect pins SCL1-SCL4 to the SCL lines on the downstream channels 1-4, respectively. It is acceptable to float any pin that will never be connected to the upstream bus. Otherwise, an external pull-up resistor or current source is required on each pin. SDA1-SDA4 (Pins 19, 22, 2, 16/Pins 17, 20, 24, 14): Serial Bus Data Output Channels 1-4. Connect pins SDA1-SDA4 to the SDA lines on downstream channels 1-4, respectively. It is acceptable to float any pin that will never be connected to the upstream bus. Otherwise, an external pull-up resistor or current source is required on each pin. ALERT1-ALERT4 (Pins 20, 24, 21, 9/Pins 18, 22, 19, 7): Fault Alert Inputs, Channels 1-4. Devices on each of the four output channels can pull their respective pin low to indicate that a fault has occurred. The LTC4306 then pulls the ALERT low to pass the fault indication on to the host. See Operation section below for the details of how ALERT is set and cleared. Connect unused fault alert inputs to VCC. Exposed Pad (Pin 25, UFD Package Only): Power Ground. Exposed Pad may be left open or connected to device ground.
6
U
U
U
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INACC OUTACC SLEW RATE DETECTOR SDA1
SLEW RATE DETECTOR
UPSTREAM DOWNSTREAM BUFFERS
SDAIN
SDA2
SDA3
INACC OUTACC 4 SLEW RATE DETECTOR
SLEW RATE DETECTOR
UPSTREAM DOWNSTREAM BUFFERS
DOWNSTREAM 1V THRESHOLD COMPARATORS
SCLIN STUCK LOW 0.52V COMPARATORS
SCL1 SCL2 SCL3 SCL4 FET1 FET2 FET3 FET4 CONN ALERT2 4 AL1-AL4 ALERT 4 FET1-FET4 ALERT LOGIC ALERT 1V THRESHOLD COMPARATORS ALERT3 ALERT4 ALERT1
READY
SCLIN
1.6V/1.52V FET1-FET4 4 TIMSET1 TIMSET0 TIMEOUT_REAL TIMEOUT_LATCH 4 CH1CONN-CH4CONN CONN_REQ PORB FAILCONN_ATTEMPT 4 4 AL1-AL4 BUS1_LOG-BUS4_LOG CONNECTION CIRCUITRY STUCK LOW TIMEOUT CIRCUITRY
+ -
100ns GLITCH FILTER
SDAIN VCC
+ -
100ns GLITCH FILTER
2pF
50k
UVLO GND
VCC
2.5V/2.35V
+ -
1s FILTER
UVLO
ENABLE
1.1V/1V
+ -
2-WIRE DIGITAL INTERFACE AND REGISTERS
VCC
1V
+ -
GPIO2 5
ADDRESS FIXED BITS "10"
ADR2 I2C ADDR 5 1 OF 27 ADR1 ADR0
VCC
INACC OUTACC
1V
+ -
GPIO1
W
BLOCK DIAGRA
SDA4
LTC4306
7
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LTC4306
OPERATIO
Register 0 (00h)
BIT NAME d7 Downstream Connected
Control Register Bit Definitions
Register 1 (01h)
TYPE* DESCRIPTION R Indicates if upstream bus is connected to any downstream buses 0 = upstream bus disconnected from all downstream buses 1 = upstream bus connected to one or more downstream buses Logic state of ALERT1 pin, noninverting Logic state of ALERT2 pin, noninverting Logic state of ALERT3 pin, noninverting Logic state of ALERT4 pin, noninverting Indicates if an attempt to connect to a downstream bus failed because the "Connection Requirement" bit in Register 2 was low and the downstream bus was low 0 = Failed connection attempt occurred 1 = No failed attempts at connection occurred Latched bit indicating if a timeout has occurred and has not yet been cleared. 0 = no latched timeout 1 = latched timeout Indicates real-time status of Stuck Low Timeout Circuitry 0 = no timeout is occurring 1 = timeout is occurring d5 d4 GPIO1 Output Driver State GPIO2 Output Driver State GPIO1 Logic State GPIO2 Logic State R/W R/W R R R BIT d7 NAME Upstream Accelerators Enable TYPE* DESCRIPTION R/W Activates upstream rise time accelerator currents 0 = upstream rise time accelerator currents inactive (default) 1 = upstream rise time accelerator currents active Activates downstream rise time accelerator currents 0 = downstream rise time accelerator currents inactive (default) 1 = downstream rise time accelerator currents active GPIO1 output driver state, noninverting, default = 1 GPIO2 output driver state, noninverting, default = 1 Not Used Logic state of GPIO1 pin, noninverting Logic state of GPIO2 pin, noninverting
d6 ALERT1 Logic State d5 ALERT2 Logic State d4 ALERT3 Logic State d3 ALERT4 Logic State d2 Failed Connection Attempt
d1 Latched Timeout
d0 Timeout Real Time
Note: Masters write to Register 0 to reset the fault circuitry after a fault has occurred and been resolved. Because Register 0 is Read-Only, no other functionality is affected. * For Type, "R/W" = Read Write, "R" = Read Only
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R R R R R d6 Downstream Accelerators Enable R/W d3-d2 Reserved d1 d0 R * For Type, "R/W" = Read Write, "R" = Read Only R
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LTC4306
OPERATIO
Register 2 (02h) BIT NAME d7 GPIO1 Mode Configure
d6 GPIO2 Mode Configure
d5 Connection Requirement
d4 GPIO1 Output Mode Configure d3 GPIO2 Output Mode Configure d2 Mass Write Enable
d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1** d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0** * For Type, "R/W" = Read Write, "R" = Read Only **Stuck bus program table TIMSET1 0 0 1 1 TIMSET0 0 1 0 1 TIMEOUT MODE Timeout Disabled (Default) Timeout After 30ms Timeout After 15ms Timeout After 7.5ms
U
Register 3 (03h)
TYPE* DESCRIPTION R/W Configures Input/Output mode of GPIO1 0 = output mode (default) 1 = input mode R/W Configures Input/Output Mode of GPIO2 0 = output mode (default) 1 = input mode R/W Sets logic requirements for downstream buses to be connected to upstream bus 0 = Bus Logic State bits (see register 3) of buses to be connected must be high for connection to occur (default) 1 = Connect regardless of downstream logic state R/W Configures GPIO1 Output Mode 0 = open-drain pull-down (default) 1 = push-pull R/W Configures GPIO2 Output Mode 0 = open-drain pull-down (default) 1 = push-pull R/W Enable Mass Write Address using address (1011 101)b 0 = Disable Mass Write 1 = Enable Mass Write (default) d2 Bus 2 Logic State R d3 Bus 1 Logic State BIT NAME d7 Bus 1 FET State TYPE* DESCRIPTION R/W Sets and indicates state of FET switches connected to downstream bus 1 0 = switch open (default) 1 = switch closed R/W Sets and indicates state of FET switches connected to downstream bus 2 0 = switch open (default) 1 = switch closed R/W Sets and indicates state of FET switches connected to downstream bus 3 0 = switch open (default) 1 = switch closed R/W Sets and indicates state of FET switches connected to downstream bus 4 0 = switch open (default) 1 = switch closed R Indicates logic state of downstream bus 1; only valid when disconnected from upstream bus 0 = SDA1, SCL1 or both are below 1V 1 = SDA1 and SCL1 are both above 1V Indicates logic state of downstream bus 2; only valid when disconnected from upstream bus 0 = SDA2, SCL2 or both are below 1V 1 = SDA2 and SCL2 are both above 1V Indicates logic state of downstream bus 3; only valid when disconnected from upstream bus 0 = SDA3, SCL3 or both are below 1V 1 = SDA3 and SCL3 are both above 1V Indicates logic state of downstream bus 4; only valid when disconnected from upstream bus 0 = SDA4, SCL4 or both are below 1V 1 = SDA4 and SCL4 are both above 1V d6 Bus 2 FET State d5 Bus 3 FET State d4 Bus 4 FET State d1 Bus 3 Logic State R d0 Bus 4 Logic State R * For Type, "R/W" = Read Write, "R" = Read Only These bits give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a "don't care" if its associated downstream bus is already connected to the upstream bus.
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LTC4306
OPERATIO
The LTC4306 is a 4-channel, 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Masters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4306 to any combination of the 4 downstream buses. Masters can also program the LTC4306 to disconnect the upstream bus from the downstream buses if the bus is stuck low. Undervoltage Lockout (UVLO) and ENABLE Functionality The LTC4306 contains undervoltage lockout circuitry that maintains all of its SDA, SCL, GPIO and ALERT pins in high impedance states until the device has sufficient VCC supply voltage to function properly. It also ignores any attempts to communicate with it via the 2-wire buses in this condition. When the ENABLE pin voltage is low (below 0.8V), all control bits are reset to their default high impedance states, and the LTC4306 ignores 2-wire bus commands. However, with ENABLE low, the LTC4306 still monitors the ALERT1-ALERT4 pin voltages and pulls the ALERT pin low if any of ALERT1-ALERT4 is low. When ENABLE is high, devices can read from and write to the LTC4306. Connection Circuitry Masters on the upstream SDAIN/SCLIN bus can write to the Bus 1 FET State through Bus 4 FET State bits of register 3 to connect to any combination of downstream channels 1 to 4. By default, the Connection Circuitry shown in the Block Diagram will only connect to downstream channels whose corresponding Bus Logic State bits in register 3 are high at the moment that it receives the connection command. If the LTC4306 is commanded to connect to multiple channels at once, it will only connect to the channels that are high. Masters can override this feature by setting the Connection Requirement bit of register 2 high. With this bit high, the LTC4306 executes connection commands without regard to the logic states of the downstream channels. Upon receiving the connection command, the Connection Circuitry will activate the Upstream-Downstream Buffers under two conditions: first, the master must be
10
U
commanding connection to one or more downstream channels, and second, there must be no stuck low condition (see Stuck Low Timeout Fault discussion). If the connection command is successful, the UpstreamDownstream Buffers pass signals between the upstream bus and the connected downstream buses. The LTC4306 also turns off its N-channel MOSFET open-drain pulldown on the READY pin, so that READY can be pulled high by its external pull-up resistor. Upstream-Downstream Buffers Once the Upstream-Downstream Buffers are activated, the functionality of the SDAIN and any connected downstream SDA pins is identical. A low forced on any connected SDA pin at any time results in all pins being low. External devices must pull the pin voltages below 0.4V worst-case with respect to the LTC4306's ground pin to ensure proper operation. The SDA pins enter a logic high state only when all devices on all connected SDA pins force a high. The same is true for SCLIN and the connected downstream SCL pins. This important feature ensures that clock stretching, clock arbitration and the acknowledge protocol always work, regardless of how the devices in the system are connected to the LTC4306. The Upstream-Downstream Buffers provide capacitive isolation between SDAIN/SCLIN and the downstream connected buses. Note that there is no capacitive isolation between connected downstream buses; they are only separated by the series combination of their switches' on resistances. While any combination of downstream buses may be connected at the same time, logic high levels are corrupted if multiple downstream buses are active and both the VCC voltage and one or more downstream bus pull-up voltages are larger than the pull-up supply voltage for another downsteam bus. An example of this issue is shown in Figure 1. During logic highs, DC current flows from VBUS1 through the series combination of R1, N1, N2 and R2 and into VBUS2, causing the SDA1 voltage to drop and current to be sourced into VBUS2. To avoid this problem, do not activate bus 1 or any other downstream bus whose pullup voltage is above 2.5V when bus 2 is active.
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LTC4306
OPERATIO
Figure 1. Example of Unacceptable Level Shifting
Rise Time Accelerators The Upstream Accelerators Enable and Downstream Accelerators Enable bits of register 1 activate the upstream and downstream rise time accelerators, respectively. When activated, the accelerators turn on in a controlled manner and source current into the pins during positive bus transitions. When no downstream buses are connected, an upstream accelerator turns on when its pin voltage exceeds 0.8V and is rising at a minimum slew rate of 0.8V/s. When one or more downstream buses are connected, the accelerator on a given pin turns on when these conditions are met: first, the pin's voltage is rising at a minimum slew rate of 0.8V/s; second, the voltages on both the upstream bus and the connected downstream buses exceed 0.8V. Note that a downstream bus's switch must be closed in order for its rise time accelerator current to be active. See the Applications Section for choosing a bus pull-up resistor value to ensure that the rise time accelerator switches turn on. Do not activate boost currents on a bus whose pull-up supply voltage VBUS is less than VCC. Doing so would cause the boost currents to source current from VCC into the VBUS supply during rising edges. Downstream Bus Connection Fault By default, the LTC4306 will only connect to downstream channels whose SDA and SCL pins are both high (above 1V) at the moment that it receives the connection command. In this case, the LTC4306 sets the Failed Connection Attempt bit of register 0 low and pulls the ALERT pin low when the master tries to connect to a low downstream
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VCC = VBUS1 = 5V SDA1 N1 SDA2 N2
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R1 10k VBUS2 = 2.5V R2 10k
channel. Note that users can write a high to the Connection Requirement bit of register 2 high to program the LTC4306 to connect to downstream channels regardless of their logic state at the moment of connection. In this case, the downstream channel connection fault never occurs. Stuck Low Timeout Fault The stuck low timeout circuitry monitors the two common internal nodes of the downstream SDA and SCL switches and runs a timer whenever either of the internal node voltages is below 0.52V. The timer is reset whenever both internal node voltages are above 0.6V. If the timer ever reaches the time programmed by Timeout Mode Bits 1 and 0 of register 2, the LTC4306 pulls ALERT low and disconnects the downstream bus(es) from the upstream bus by de-biasing the Upstream-Downstream Buffers. Note that the downstream switches remain in their existing state. The Timeout Real-Time bit of register 0 indicates the realtime status of the stuck low situation. The Latched Timeout Bit of register 0 is a latched bit that is set high when a timeout occurs. External Faults on the Downstream Channels When a slave on downstream bus 1 pulls the ALERT1 pin below 1V, the LTC4306 passes this information to the master on the upstream bus by pulling the ALERT pin low. The same is true for the other three downstream buses. Each bus has its own dedicated fault bit in Register 0, so that masters can read Register 0 to determine which buses have faults. ALERT Functionality and Fault Resolution When a fault occurs, the LTC4306 pulls the ALERT pin low, as described previously. The procedure for resolving faults depends on the type of fault. If a master on the upstream bus is communicating with devices on a downstream bus via the Upstream-Downstream Buffer circuitry--channel 1, for example--and a device on this bus pulls the ALERT1 pin low, the LTC4306 acts transparently, and the master communicates directly with the device that caused the fault via the upstream-downstream buffer circuitry to resolve the fault.
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LTC4306
OPERATIO
In all other cases, the LTC4306 communicates with the master to resolve the fault. After the master broadcasts the Alert Response Address (ARA), the LTC4306 will respond with its address on the SDAIN line and release the ALERT pin. The ALERT line will also be released if the LTC4306 is addressed by the master. The ALERT signal will not be pulled low again until a different type of fault has occurred or the original fault is cleared and it occurs again. Figure 2 shows the details of how the ALERT pin is set and reset. The downstream bus connection fault and faults that occur on unconnected downstream buses are grouped together and generate a single signal to drive ALERT. The stuck low timeout fault has its own dedicated pathway to ALERT; however, once a stuck low occurs, another one will not occur until the first one is cleared. For these reasons, once the master has established the LTC4306 as the source of the fault, it should read register 0 to determine the specific problem, take action to solve the problem, and clear the fault promptly. All faults are cleared by writing a dummy data byte to register 0, which is a read-only register. For example, assume that a fault occurs, the master sends out the ARA, and the LTC4306 successfully writes its address onto SDAIN and releases its ALERT pin. The master reads register 0 and learns that the ALERT2 logic state bit is low. The master now knows that a device on downstream bus 2 has a fault and writes to register 3 to
FAULT ON DISCONNECTED DOWNSTREAM BUS DOWNSTREAM BUS CONNECTION FAULT VCC D WRITE REGISTER 0 ADDRESS LTC4306 LTC4306 RESPONDS TO ARA STUCK BUS VCC D WRITE REGISTER 0 RD RD
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connect to bus 2, so that it can communicate with the source of the fault. At this point, the master writes to register 0 to clear the LTC4306 fault register. I2C Device Addressing Twenty-seven distinct bus addresses are configurable using the three state ADR0, ADR1 and ADR2 pins. Table 1 shows the correspondence between pin states and addresses. Note that address bits a6 and a5 are internally configured to 1 and 0 respectively. In addition, the LTC4306 responds to two special addresses. Address (1011 101) is a mass write used to write all LTC4306's, regardless of their individual address settings. The mass write can be masked by setting the Mass Write Enable bit of register 2 to zero. Address (0001 100) is the SMBus Alert Response Address. Figure 3 shows data transfer over a 2-wire bus. Supported Commands Users must write to the LTC4306 using the SMBus Write Byte protocol and read from it using the Read Byte protocol. During fault resolution, the LTC4306 also supports the Alert Response Address protocol. The formats for these protocols are shown in Figure 4. Users must follow the Write Byte protocol exactly to write to the LTC4306; if a Repeated Start Condition is issued before a Stop Condition, the LTC4306 ignores the attempted write, and its control bits remain in their preexisting state. When
ALERT Q FAULT ON CONNECTED DOWNSTREAM BUS Q
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Figure 2. Setting and Resetting the ALERT Pin
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LTC4306
OPERATIO
DESCRIPTION Mass Write Alert Response 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Table 1. LTC4306 I2C Device Addressing
HEX DEVICE ADDRESS h BA 19 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 A6 A8 AA AC AE B0 B2 B4 a6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY DEVICE ADDRESS a4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 a3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 a2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 a1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 a0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X ADR2 X X L L L L L L L L NC NC NC NC NC NC NC NC H H H H H H H H H L NC LTC4306 ADDRESS PINS ADR1 X X NC H NC NC L H L L NC H NC NC L H L L NC H NC NC L H L L H H H ADR0 X X L NC NC H L H NC H L NC NC H L H NC H L NC NC H L H NC H L L L
users follow the Write Byte protocol exactly, the new data contained in the Data Byte is written into the register selected by bits r1 and r0 on the Stop Bit. General Purpose Input/Outputs (GPIOs) The LTC4306 provides two general purpose input/output pins (GPIOs) that can be configured as logic inputs, opendrain outputs or push-pull outputs. The GPIO1 and GPIO2
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Mode Configure bits in register 2 determine whether the GPIOs are used as inputs or outputs. When the GPIOs are used as outputs, the GPIO1 and GPIO2 Output Mode Configure bits of register 2 configure the GPIO outputs either as open-drain N-channel MOSFET pull-downs or push-pull stages. In push-pull mode, at VCC = 3.3V, the typical pull-up impedance is 670 and the typical pull-down impedance
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LTC4306
OPERATIO
SDA
SCL S
START CONDITION
1 START
is 35, making the GPIO pull-downs capable of driving LEDs. At VCC = 5V, the typical pull-up impedance is 320 and the typical pull-down impedance is 20. In opendrain output mode, the user provides the logic high by connecting a pull-up resistor between the GPIO pin and an external supply voltage. The external supply voltage can range from 1.5V to 5.5V independent of the VCC voltage. In input mode, the GPIO input threshold voltage is 1V. The GPIO1 and GPIO2 Logic State bits in register 1 indicate the logic state of the two GPIO pins. The logiclevel threshold voltage for each pin is 1V. The GPIO1 and GPIO2 Output Driver State bits in register 1 indicate the logic state that the LTC4306 is attempting to write to the GPIO pins. This is useful when the GPIOs are being used
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a6-a0 d7-d0 d7-d0 1-7 8 9 1-7 8 9 1-7 8 9 P ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION
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Figure 3. Data Transfer Over I2C or SMBus
1 START 7 10 a4-a0 SLAVE ADDRESS 1 WR 0 1 ACK S 0 8 XXXXXX r1r0 REGISTER 1 ACK S 0 8 d7-d0 DATA BYTE 1 ACK S 0 1 STOP
WRITE BYTE PROTOCOL 7 10 a4-a0 SLAVE ADDRESS 1 WR 0 1 ACK S 0 8 XXXXXX r1r0 REGISTER 1 ACK S 0 1 START 7 10 a4-a0 SLAVE ADDRESS 1 RD 1 1 ACK S 0 8 d7-d0 DATA BYTE 1 ACK M 1 1 STOP
READ BYTE PROTOCOL 1 S 7 0001 100 1 RD 1 1 ACK S 0 8 DEVICE ADDRESS 1 ACK M 1 1 P
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ALERT RESPONSE ADDRESS PROTOCOL
Figure 4. Protocols Accepted by LTC4306
in open-drain output mode and one or more external devices are connected to the GPIOs. If the LTC4306 is trying to write a high to a GPIO pin, but the pin's actual logic state is low, then the LTC4306 knows that the low is being forced by an external device. Glitch Filters The LTC4306 provides glitch filters on the SDAIN and SCLIN pins as required by the I2C Fast Mode (400kHz) Specification. The filters prevent signals of up to 50ns (minimum) time duration and rail-to-rail voltage magnitude from passing into the two-wire bus digital interface circuitry.
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LTC4306
OPERATIO
Fall Time Control Per the I2C Fast Mode (400kHz) Specification, the twowire bus digital interface circuitry provides fall time control when forcing logic lows onto the SDAIN bus. The fall time always meets the limits: (20 + 0.1 * CB) < tf < 300ns
APPLICATIO S I FOR ATIO
Design Example
A typical LTC4306 application circuit is shown in Figure 5. The circuit illustrates the level-shifting, multiplexer/switch and capacitance buffering features of the LTC4306. In this application, the LTC4306 VCC voltage and downstream bus 1 are powered from a 3.3V supply voltage; downstream bus 4 is powered from 5V, and the upstream bus is powered from 2.5V. Channels 2 and 3 are omitted for simplicity. The following sections describe a methodology for choosing the external components in Figure 5. SDA, SCL Pull-Up Resistor Selection The pull-up resistors on the SDA and SCL pins must be strong enough to provide a minimum of 100A pull-up current, per the SMBus Specification. In most systems,
VBACK = 2.5V
R1 10k
R2 10k
MICROCONTROLLER
R10 1k VCC
D1
Figure 5. A Level Shifting Circuit
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where tf is the fall time in ns and CB is the equivalent bus capacitance in pF. Whenever the Upstream-Downstream Buffer Circuitry is active, its output signal will meet the fall time requirements, provided that its input signal meets the fall time requirements. the required minimum strength of the pull-up resistors is determined by the minimum slew requirement to guarantee that the LTC4306's rise time accelerators are activated during rising edges. At the same time, the pull-up value should be kept low to maximize the logic low noise margin and minimize the offset voltage of the Upstream-Downstream Buffer circuitry. The LTC4306 is designed to function for a maximum DC pull-up current of 4mA. If multiple downstream channels are active at the same time, this means that the sum total of the pull-up currents from these channels must be less than 4mA. At supply voltages of 2.7V and 5.5V, pull-up resistor values of 10k work well for capacitive loads up to 215pF and 420pF, respectively. For larger bus capacitances, refer to equation (1) below. The LTC4306 works with capacitive loads up to 2nF.
VCC = VBUS1 = 3.3V C1 0.01F R3 10k 6 VCC 16 4 SCL1 SCLIN 17 2 SDA1 SDA1N 18 1 ALERT ALERT1 R4 10k R5 10k R6 10k SFP MODULE 1 ADDRESS = 1111 000 LTC4306UFD 8 GPIO1 15 SCL4 14 SDA4 7 ALERT4
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VBUS4 = 5V
12 ADR2 11 ADR1 10 ADR0 3 GND
R7 10k
R8 10k
R9 10k SFP MODULE 4 ADDRESS = 1111 001
ADDRESS = 1000 100
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LTC4306
APPLICATIO S I FOR ATIO
Assume in Figure 5 that the total parasitic bus capacitance on SDA1 due to trace and device capacitance is 100pF. To ensure that the boost currents are active during rising edges, the pull-up resistor must be strong enough to cause the SDA1 pin voltage to rise at a rate of 0.8V/s as the pin voltage is rising above 0.8V. The equation is:
ns ( VBUSMIN - 0 . 8 V) * 1250 V (1) RPULL -UP,MAX [k ] = CBUS [pF ]
where VBUSMIN is the minimum operating pull-up supply voltage, and CBUS is the bus parasitic capacitance. In our example, VBUS1 = VCC = 3.3V, and assuming 10% supply tolerance, VBUS1MIN = 2.97V. With CBUS = 100pF, RPULL-UP,MAX = 27.1k. Therefore, we must choose a pullup resistor smaller (i.e., stronger pull-up) than 27.1k, so a 10k resistor works fine. ALERT, READY and GPIO Component Selection The pull-up resistors on the ALERT and READY pins must provide a maximum pull-up current of 3mA, so that the LTC4306 is capable of holding the pin at logic low voltages below 0.4V. When choosing LEDs to be driven by the LTC4306's GPIO pins, make sure that the required LED sinking current is less than 5mA, and add a currentlimiting resistor in series with the LED. Level Shifting Considerations In the design example of Figure 5, the LTC4306 VCC voltage is less than or equal to both of the downstream bus pull-up voltages, so buses 1 and 4 can be active at the same time. Likewise, the rise time accelerators can be turned on for the downstream buses, but must never be activated on SCLIN and SDAIN, because doing so would result in significant current flow from VCC to VBACK during rising edges. Other Application Circuits Figure 6 illustrates how the LTC4306 can be used to expand the number of devices in a system by using nested addressing. Each I/O card contains a temperature sensor
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having device address 1001 000. If the four I/O cards were plugged directly into the backplane, the four sensors would require four unique addresses. However, if masters use the LTC4306 in multiplexer mode, where only one downstream channel is connected at a time, then each I/O card can have a device with address 1001 000 and no problems will occur. Figures 7 and 8 show two different methods for hotswapping I/O cards onto a live two-wire bus using the LTC4306. The circuitry of Figure 7 consists of an LTC4306 residing on the edge of an I/O card having four separate downstream buses. Connect a 200k resistor to ground from the ENABLE pin and make the ENABLE pin the shortest pin on the connector, so that the ENABLE pin remains at a constant logic low while all other pins are connecting. This ensures that the LTC4306 remains in its default high impedance state and ignores connection transients on its SDAIN and SCLIN pins until they have established solid contact with the backplane 2-wire bus. In addition, make sure that the ALERT connector pin is shorter than the VCC pin, so that VCC establishes solid contact with the I/O card pull-up supply pin and powers the pull-up resistors on ALERT1-ALERT4 before ALERT makes contact. Figure 8 illustrates an alternate SDA and SCL hot-swapping technique, where the LTC4306 is located on the backplane and an I/O card plugs into downstream channel 4. Before plugging and unplugging the I/O card, make sure that channel 4's downstream switch is open, so that it does not disturb any 2-wire transaction that may be occurring at the moment of connection/disconnection. Note that pull-up resistor, R17, on ALERT4 should be located on the backplane and not the I/O card to ensure proper operation of the LTC4306 when the I/O card is not present. The pullup resistors on SCL4 and SDA4, R15 and R16 respectively, may be located on the I/O card, provided that downstream bus 4 is never activated when the I/O card is not present. Otherwise, locate R15 and R16 on the backplane.
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LTC4306
APPLICATIO S I FOR ATIO
VCC R2 10k R3 10k R4 10k
P
R1 1k
LED
VCC OPEN 11 10 3
Figure 6. Nested Addressing Application
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R5 10k C1 0.01F 6 VCC SCLIN SDAIN 5 1 13 8 9 ENABLE ALERT READY GPI01 GPI02 SCL3 SDA3 12 ALERT3 ADR2 ADR1 ADR0 GND SCL4 SDA4 ALERT4 15 14 7 R12 10k R13 10k R14 10k TEMPERATURE SENSOR ADDRESS = 1001 000 SCL2 SDA2 ALERT2 LTC4306UFD 21 20 22 SCL1 SDA1 ALERT1 16 17 18 TEMPERATURE SENSOR ADDRESS = 1001 000 R6 10k R7 10k R8 10k 4 2 R9 10k R10 10k R11 10k TEMPERATURE SENSOR ADDRESS = 1001 000 23 24 19 R15 10k R16 10k R17 10k TEMPERATURE SENSOR ADDRESS = 1001 000 ADDRESS = 1010 000
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LTC4306
APPLICATIO S I FOR ATIO
VCC
R4 10k
R5 10k 4 SCLIN SDAIN ENABLE
P
VCC VCC R3 10k R18 200k
VCC OPEN
BACKPLANE CONNECTOR
CARD CONNECTOR
Figure 7. Hot-Swapping Application
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C1 0.01F 6 VCC SCL1 SDA1 ALERT1 16 17 18 R6 10k R7 10k R8 10k CARD_SCL1 CARD_SDA1 CARD_ALERT1 2 5 VBUS2 21 20 22 R9 10k R10 10k R11 10k CARD_SCL2 CARD_SDA2 CARD_ALERT2 SCL2 1 SDA2 ALERT ALERT2 LTC4306UFD SCL3 SDA3 12 11 10 3 ALERT3 ADR2 ADR1 ADR0 GND SCL4 SDA4 ALERT4 15 14 7 23 24 19 R12 10k R13 10k R14 10k CARD_SCL3 CARD_SDA3 CARD_ALERT3 R15 10k R16 10k R17 10k CARD_SCL4 CARD_SDA4 CARD_ALERT4 R2 10k READY GPI01 GPI02 ADDRESS = 1010 000 13 8 9
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LED
R1 1k
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LTC4306
PACKAGE DESCRIPTIO U
UFD Package 24-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1696)
2.65 0.10 (2 SIDES) 4.00 0.10 (2 SIDES) 0.75 0.05 R = 0.115 TYP 23 24 PIN 1 NOTCH R = 0.30 TYP 0.70 0.05 4.50 0.05 3.10 0.05 2.65 0.05 (2 SIDES) 5.00 0.10 (2 SIDES) 3.65 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.40 0.05 1 2 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.65 0.05 (2 SIDES) 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
(UFD24) QFN 0505
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
GN Package 24-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.337 - .344* (8.560 - 8.738)
.045 .005
24 23 22 21 20 19 18 17 16 15 1413
.033 (0.838) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0165 .0015 RECOMMENDED SOLDER PAD LAYOUT
.0250 BSC
1
23
4
56
7
8
9 10 11 12
.015 .004 x 45 (0.38 0.10) .0075 - .0098 (0.19 - 0.25) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE
.0532 - .0688 (1.35 - 1.75)
.004 - .0098 (0.102 - 0.249)
0 - 8 TYP
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN24 (SSOP) 0204
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC4306
APPLICATIO S I FOR ATIO
VCC = 3.3V R2 10k R3 10k R4 10k
MICROCONTROLLER
VCC R1 1k LED
OPEN
Figure 8. Downstream Side Hot-Swapping Application
RELATED PARTS
PART NUMBER LTC1380/LTC1393 LTC1427-50 LTC1694/LTC1694-1 LT(R)1786F LTC1695 LTC1840 LTC4300A-1/LTC4300A-2 LTC4300A-3 LTC4301 LTC4301L DESCRIPTION Single-Ended 8-Channel/Diffierential 4-Channel Analog Mux with SMBus Interface Micropower, 10-Bit Current Output DAC with SMBus Interface SMBus Accelerator COMMENTS Low RON: 35 Single-Ended/70 Differential, Expandable to 32 Single or 16 Differential Channels Precision 50A 2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers Up at Zero or Midscale Improved SMBus/I2C Rise Time, Ensures Data Integrity with Multiple SMBus/I2C Devices 1.25A, 200kHz, Floating or Grounded Lamp Configurations 0.75 PMOS 180mA Regulator, 6-Bit DAC Two 100A 8-Bit DACs, Two Tach Inputs, Four GPIO Isolates Backplane and Card Capacitances Provides Level Shifting and Enable Functions Supply Independent Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN Recover Stuck Buses with Automatic Clocking 2 Selectable Downstream Buses, Stuck Bus Disconnect, Rise Time Accelerators, Fault Reporting, 10kV HBM ESD Tolerance
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SMBus Controlled CCFL Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM Dual I2C Fan Speed Controller Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer Supply Independent Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation LTC4303/LTC4304 How Swappable Bus Buffers with Stuck Bus Recovery LTC4305 2-Channel 2-Wire Multiplexer with Capacitance Buffering ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
www.linear.com
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R5 10k VCC SCLIN SDAIN ENABLE ALERT READY GPI01 GPI02 SCL3 SDA3 ALERT3 ADR2 ADR1 ADR0 GND SCL4 SDA4 ALERT4
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C1 0.01F SCL1 SDA1 ALERT1
R6 10k
R7 10k
R8 10k TEMPERATURE SENSOR
VCC2 = 5V R9 10k SCL2 SDA2 ALERT2 VCC3 = 2.5V R12 10k R13 10k R14 10k TEMPERATURE SENSOR VCC4 = 3.3V R15 10k R16 10k R17 10k VOLTAGE MONITOR I/O CARD R10 10k R11 10k VOLTAGE MONITOR
LTC4306UFD
ADDRESS = 1010 000
LT/LWI/TP 0805 500 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2005

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